EEPROM flash memories are known in the prior art as large-capacity multifunctional nonvolatile semiconductor memories. In this type of semiconductor memories, microfabricated ultra-fine circuitry of less than 100 nm has been achieved on a flat surface or plane due to recent advances in lithography technologies and etching techniques. As far as considerations on the plane are concerned, it is a must for enlargement of the memory capacity to further advance microfabrication or miniaturization in order to increase a cell number per unit area. However, such further miniaturization is not easy.
In order to increase the memory capacity without advancing the miniaturization, there is employed a method for sealing a plurality of stacked memory chips together into a package or alternatively a method of stacking or laminating memory cell arrays on or above silicon to thereby provide a three-dimensional memory chip. However, the conventionally conceived cell array stacking techniques are to simply overlie planar cell arrays. In this case, although if the number of such stacked or laminated layers is N then the resultant storage capacity is N times greater than a planar cell array, accessing is done separately in units of respective layers; thus, simultaneous access to a plurality of layers has not been easily achievable.
On the other hand, a phase change memory has been proposed which is expected as a nonvolatile memory for the future use and which utilizes a phase transition between crystalline and amorphous states in chalcogenide glass material (for example, see Jpn. J. Appl. Phys. Vol. 39 (2000) PP. 6157-6161 Part 1. No. 11, November 2000 “Submicron Nonvolatile Memory Cell Based on Reversible Phase Transition in Chalcogenide Glasses” Kazuya Nakayama et al). This utilizes the fact that the chalcogenide's resistance ratio of its amorphous state to crystalline state is as large as 100:1 or greater and stores therein such different resistance value states as binary data. The chalcogenide's phase change is reversible, wherein such change is well controllable by an appropriate heating technique or method, which in turn is controllable by the amount of a current flowing in this material.
In the case of designing such a phase change memory in ultra-large scale, unwanted variations or irregularities in distributions of low resistance values and high resistance values of memory cells within a cell array become larger so that how to provide the required read/write margins becomes an important technical issue.